Add the Verilog code
458 USD 
https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md
After processing: Each module in its own file, the file name corresponds to the name of the module with extension .v All modules are installed with the nominal destination of the ports Returns are followed as recommended in the link above All signals are announced before they are used (wire + signal name) The executor must have experience working with Verilog.You need to use software tools such as Sigasi or your own written script.Reduce manual work to a minimum to avoid errors.Code Volume: 31000 lines of code including comments of 210 modules and approximately the same instances
Example of the code in the application.Thank you for your interest and hope for successful cooperation!
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